The present invention relates to a method of forming a semiconductor device such as a semiconductor integrated circuit, and more particularly to a method of hydrogen annealing a semiconductor substrate for forming a semiconductor device such as a semiconductor integrated circuit in order to improve device performance and reliability.
To form semiconductor integrated circuits such as memory and logic circuits, various devices are formed on a substrate and then an inter-layer insulator is formed over the substrate, before the substrate is subjected to a hydrogen anneal in a hydrogen-nitrogen atmosphere at a temperature of 400xc2x0 C.
This hydrogen anneal is effective for improvements in characteristics of electrical connections between metal interconnections and also characteristics of electrical connections between a semiconductor substrate and a metal interconnection. The hydrogen anneal is also effective for improvements in performances and reliability of the semiconductor device and an improvement in yield of the semiconductor device.
In case of dynamic random access memory, interface states are present on an interface of silicon substrate and a silicon oxide film such as a field oxide film and a gate oxide film. A leakage of current from a diffusion layer through this interface state to the substrate is caused, whereby a hold characteristic of the DRAM is deteriorated. The interface state also causes variation in characteristics of the device such as transistors, for example, variations in a threshold voltage and a current-voltage characteristic from designed values. This interface state makes it difficult to improve the yield and reliability of the semiconductor device. The hydrogen anneal is effective to obtain desired characteristics of the transistors such as threshold voltage and current-voltage characteristic for other semiconductor devices than the DRAM, for example, logic devices. The interface states are caused by dangling bond of silicon near the interface between silicon and silicon interface. The hydrogen anneal supplies hydrogen to the interface between silicon oxide so that the dangling bond is terminated with hydrogen supplied, whereby the interface state is reduced.
In recent years, scaling down and increase in density of integration of the semiconductor integrated circuits have been on the increase. Further, a multilayer structure has been on development. Furthermore, new multilayer structures, electrode materials, interconnection materials and insulator materials have been developed and used. These new conditions make it difficult to penetrate and diffuse hydrogen to the interface between silicon and silicon oxide through the hydrogen anneal. In order to solve this difficulty, it is necessary to make an anneal time longer and to rise an anneal temperature. If the anneal time becomes longer, then a problem with reduction in productivity of the semiconductor device is raised. If the anneal temperature is risen, spikes or hillocks are caused on metal interconnection such as an aluminum interconnection, whereby the reliability is deteriorated. Furthermore, the temperature increase does not necessarily cause desired effects of the hydrogen anneal.
The permeability of hydrogen depends upon materials of the device. For example, permeability of hydrogen to silicon oxide films such as the inter-layer insulator and the field oxide film are relatively high. A permeability of silicon nitride film which may often be used as an etching stopper and a dielectric film of a capacitor as well as a contamination control film is low. Particularly, a silicon nitride film deposited by a low pressure chemical vapor deposition method has a high film density, for which reason the silicon nitride film serves as a diffusion barrier to diffusion of hydrogen.
Metal materials such as aluminum for metal interconnections absorb hydrogen. Barrier material materials such as Ti and TiN also absorb hydrogen. Further, polysilicon used for interconnection and electrodes also absorb hydrogen. Namely, hydrogen is absorbed into the metal interconnection materials, the barrier metal materials, and polysilicon whereby the diffusion rate is remarkable reduced until the absorption is saturated to allow hydrogen to permeate those materials.
On the other hand, it is possible to consider that hydrogen penetrates from a bottom of a substrate. However, in recent years, a wafer diameter has been on the increase whereby a thickness of the wafer has also been on the increase. For example, 6-inch wafer has a thickness of 675 micrometers. 8-inch wafer has a thickness of 725 micrometers. 12-inch wafer has a thickness of over 770 micrometers. The increase in thickness of the wafer means that the necessary diffusion depth is increased, thereby making it difficult to penetrate hydrogen from the substrate bottom surface to the interface between silicon and silicon oxide. Further, when a polysilicon film and a silicon nitride film which serve as diffusion barriers to hydrogen are formed, those films are also formed or adhered on the bottom surface of the substrate, whereby it is no longer possible that hydrogen is diffused from the bottom surface of the substrate to the interface between silicon and silicon oxide. Furthermore, in case, a polysilicon film which serves as the diffusion barrier to hydrogen is formed on the bottom surface of the substrate for extrinsic gettering, whereby it is also no longer possible that hydrogen is diffused from the bottom surface of the substrate to the interface between silicon and silicon oxide. Moreover, the deep diffusion depth from the bottom surface of the substrate needs a high temperature hydrogen anneal.
The difficulty in application of the hydrogen anneal to the advanced semiconductor devices will be described with reference to the drawings. FIG. 1A is a fragmentary plan view illustrative of a stacked DRAM. FIG. 1B is a fragmentary cross sectional elevation view illustrative of a stacked DRAM taken along a Bxe2x80x94B line of FIG. 1A. FIG. 1C is a fragmentary cross sectional elevation view illustrative of a stacked DRAM taken along a Cxe2x80x94C line of FIG. 1A. Field oxide films 2 are selectively formed on a surface of a p-type silicon substrate 1 which has a predetermined crystal orientation. Silicon nitride films 6 are formed over the field oxide films 2. Diffusion layers 5 are selectively formed in an active region of the silicon substrate 1 defined by the field oxide film 2. Gate oxide films 4 of silicon oxide are formed on the active region of the silicon substrate 1. Gate electrodes 3 are formed on the gate oxide films 4. Each gate of the electrodes 3 comprises laminations of a n-type polysilicon film and a tungsten silicide film which are not illustrated. The diffusion layers 5 are self-aligned to the gate electrodes 3 and the field oxide films 2. Silicon nitride films 6 are formed on side walls of the gate electrodes 3. n-type polysilicon pads 9 are formed on the diffusion layers 5 and between the side wall silicon nitride films 6. The n-type polysilicon pads 9 are formed by an anisotropic selective epitaxial growth. A silicon oxide interlayer insulator 7 is formed over the gate electrodes 3, the side wall silicon nitride films 6. Contact holes are formed in the silicon oxide inter-layer insulator 7, so that the contact holes are positioned just over the n-type polysilicon pads 9. n-type polysilicon contacts 8 are filled within the contact holes so that the n-type polysilicon contacts 8 are made into contact with the n-type polysilicon pads 9, whereby the n-type polysilicon contacts 8 are electrically connected through the n-type polysilicon pads 9 to the diffusion layers 5. Capacitive bottom electrodes 10 are selectively formed over the silicon oxide inter-layer insulator 7, so that the capacitive bottom electrodes 10 are made into contact with the n-type polysilicon contacts 8, whereby the capacitive bottom electrodes 10 are electrically connected through the n-type polysilicon pads 9 and the n-type polysilicon contacts 8 to the diffusion layers 5. The capacitive bottom electrodes 10 are made of polysilicon. A capacitive insulating film 11 is formed on top and side surfaces of the capacitive bottom electrodes 10 and on top surfaces of the silicon oxide inter-layer insulator 7. The capacitive insulating film 11 comprises laminations of a silicon oxide film, a silicon nitride film and a silicon oxide film. A capacity top electrode 12 made of polysilicon is formed on the capacitive insulating film 11. Further, an additional inter-layer insulator is not illustrated is formed over the capacitive top electrode 12. Bit lines not illustrated are further formed over the additional inter-layer insulator. The capacitive bottom electrodes 10 are divided for every transistors formed on the surface of the substrate 1. The capacitive top electrode 12 are divided for every cell array units.
The above substrate for the stacked DRAM is then subjected to the hydrogen anneal. Hydrogen atoms supplied from the hydrogen atmosphere are first absorbed into the bit lines which are made of polysilicon. The remaining hydrogen atoms are then absorbed into the polysilicon capacitive top electrode 12. The remaining hydrogen atoms penetrate through the inter-layer insulator 7 and then reach interfaces between the top surface of the silicon substrate 1 and the gate oxide films 4 and the interfaces between the top surface of the silicon substrate 1 and the field oxide films 2. Even illustration is omitted, if the stacked DRAM has a capacitor over bit line structure where the polysilicon bit lines are provided between levels of the capacitive bottom electrodes 10 and the transistors or the gate electrodes 3, the remaining hydrogen atoms are absorbed into these polysilicon bit lines.
As the increase in the high density of the integration of the semiconductor devices and the scaling down thereof cause that occupied areas of the bit lines and word lines in a unit area are increased and further a distance between the adjacent cell arrays is made narrow. Those structures make it difficult to have hydrogen to reach the interface between silicon and silicon oxide by the hydrogen anneal.
In 16M-bit DRAM having a capacitor under bit line structure, contacts are formed between the bit lines and the diffusion layers in the substrate. These contacts serve as diffusion paths of hydrogen. In 16M-bit shrinking DRAM having the capacitor over bit line structure, the bit lines are positioned under the capacitive bottom electrodes, for which reason no contact is formed in the opening, whereby diffusion paths are present in gaps between the capacitive bottom electrodes. The 64M-bits DRAM or 64M-bits shrinking DRAM is further scaled down and has a higher density of integration, whereby gaps between the bit lines and the word lines as well as gaps between the capacitive bottom electrodes are made further narrow.
FIG. 2 is a fragmentary cross sectional elevation view illustrative of a stacked DRAM having a self-aligned contact structure and a capacitor over bit line structure in a unit of one of the capacitive top electrodes. FIG. 3 is a fragmentary plan view illustrative of a DRAM chip of FIG. 2. A silicon nitride film 6 is formed over gate electrodes 3 and field oxide films 2 in order to protect the gate electrodes 3 and the field oxide films 2 from a dry etching process to form contact holes in an inter-layer insulator 7 over the field oxide film 2 and the gate electrodes 4. The silicon nitride film 6 is selectively removed under the contact holes before contacts 8 are formed in the contact holes so that the contacts 8 are made into contact with surfaces of diffusion layers 5 in a silicon substrate 1. The bottom surface of the silicon substrate 1 is also covered by or adhered with a silicon nitride film at the same time when the silicon nitride film 6 is formed over the gate electrodes 4 and the field oxide films 2. Interfaces between the silicon substrate 1 and the field oxide films 2 and interfaces between the silicon substrate 1 and the gate oxide films 3 are shielded by the silicon nitride films which serve as the diffusion barriers to hydrogen supplied from the hydrogen atmosphere in the hydrogen anneal, for which reason it is difficult to have hydrogen to reach those interfaces.
Further, capacitive bottom electrodes 10 are provided for every transistors whilst capacitive top electrodes 11 are provided for every cell array units, for which reason diffusion path of hydrogen is only in gaps between the capacitive top electrodes 12.
Further more, the DRAM has the capacitance over bit line structure, wherein polysilicon bit lines 13 are provided at a level between the capacitive bottom electrodes 10 and the transistors. The hydrogen atoms having penetrated through the gaps between the capacitive top electrodes 10 are further absorbed into the polysilicon bit lines 13.
FIG. 4 is a diagram illustrative of a variation in leak current over a hydrogen anneal time when a silicon substrate of FIG. 1 is subjected to a hydrogen anneal in the conventional method. The anneal is carried out in a hydrogen atmosphere of a hydrogen to nitrogen ratio of 1:1 under atmospheric pressure at a constant temperature of 400xc2x0 C. The leakage of current is measured under conditions that transistors of all unit cell blocks are connected in parallel. Four types of the stacked DRAMs are subjected to the above hydrogen anneal to measure the leakage of current. The first type of DRAM (a) is 16M-bits DRAM. The second type of DRAM (b) is 16M-bits shrinking DRAM. The third type of DRAM (c) is 64M-bits DRAM. The fourth type of DRAM (d) is 64M-bits shrinking DRAM. FIG. 4 shows that the advanced higher density DRAM such as the 64M-bits shrinking DRAM needs longer time hydrogen anneal to suppress the leakage of current.
FIG. 5 is a diagram illustrative of variation in reverse current versus reverse voltage of each of a first type stacked DRAM (1) having a self-aligned contact structure and a second type stacked DRAM (2) free of any self-aligned contact structure after the first and second type DRAMs have been subjected to the hydrogen anneals. The hydrogen anneal is carried out at a hydrogen-nitrogen atmosphere of a hydrogen to nitrogen ratio of 1:1 at a constant temperature of 400xc2x0 C. under an atmospheric pressure. In order to measure the reverse current, a reverse bias is applied to a p-n junction between contacts and substrate, where the contacts have a diameter of 0.5 micrometers and are aligned to form an array. The first type stacked DRAM (1) having the self-aligned contact structure is subjected to the hydrogen anneal for a longer time, for example, 240 minutes whilst the second type stacked DRAM (2) free of any self-aligned contact structure is subjected to the hydrogen anneal for a shorter time, for example, 40 minutes. The leakage of reverse current of the first type stacked DRAM (1) having the self-aligned contact structure is remarkably larger than the leakage of reverse current of the second type stacked DRAM (2) free of any self-aligned contact structure. This shows that it is difficult to have hydrogen penetrate and diffuse to reach the interface between silicon and silicon oxide of the first type stacked DRAM (1) as compared to the second type stacked DRAM (2).
In the above circumstances, it had been required to develop a novel method of hydrogen anneal to a substrate free from the above problem.
Accordingly, it is an object of the present invention to provide a novel method of hydrogen anneal to a substrate free from the above problems.
It is a further object of the present invention to provide a novel method of hydrogen anneal to a substrate, which is capable of improvement in characteristic of a semiconductor device.
It is a still further object of the present invention to provide a novel method of hydrogen anneal to a substrate, which is capable of improvement in reliability of a semiconductor device.
It is yet a further object of the present invention to provide a novel method of hydrogen anneal to a substrate, which is capable of improvement in yield of a semiconductor device.
The present invention provides a method of carrying out a hydrogen anneal to a substrate having an interface between different materials provided that an annealing temperature is maintained higher than a hydrogen-eliminating initiation temperature, wherein a temperature of a furnace is controlled to be not higher than the hydrogen-eliminating initiation temperature until the substrate is taken out from the furnace after the hydrogen anneal is carried out. The hydrogen-eliminating initiation temperature is defined to be a temperature at which hydrogen having once terminated dangling bonds of interface states on an interface between different materials are initiated to be eliminated. The above novel temperature control is made in order to prevent hydrogen from being eliminated from dangling bonds of interface states on the interface, so that no interface state is formed on the interface, whereby a sufficient reduction in amount of the interface states on the interface is obtained, resulting in improvements in device performances and characteristics and reliability thereof as well as an improvement in the yield of the semiconductor devices.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.